Research Achievements and Proto-Memoirs: David J Greaves

WHAT I DID MODERN IMPACT At my sixth form College a number of so-called `GPIB Combiners' were built to my design. These allowed multiple IEEE-488 bus masters to share a single set of peripherals. Therefore, the printers and floppy-disk units became fileservers for a six or so Commodore PET computers. I also built a GPIB interface card for the SWTC 6800-based systems so that machine could join this early LAN. All personal computers are today connected to LAN networks.     Title and masthead from Wireless World article, 1984.     Typical LAN setup from a decade later.

My core design was published in Wireless World in April 1984 and, at that time, two commercial companies had started making these devices, including a company started by my physics teachers. (PROJECT : www.bigbrownbus.com/koo.corpus.cam.ac.old/projects/gpibcombiner/gpibcombiner.html)

WHAT I DID MODERN IMPACT I used an 8088 micrprocessor (which was just out and being used in the first IBM PCs in the same year) to scan the keyboard and front panel controls. I made a high-performance (5 MIPS) processor from discrete TTL to generate the waveforms. For 8-note polyphony, only ten or so instructions were possible per rendered sample of an instrument. This unit also had MIDI input and output, which was brand new at the time. Nearly all keyboard synthesiers currently in production are digital. Today's devices support a mixture of sample playing and algorithmic synthesis. Many of the remainder have digitally controlled pitch oscillators followed by analogue tone shaping.     A photo of the synthesier and the block diagram of the TTL processor from the Wireless World article.     The Yamaha DX7 Synthesiser

(PROJECT : www.bigbrownbus.com/koo.corpus.cam.ac.old/projects/digipoly/index.html)

WHAT I DID MODERN IMPACT From Prof P Raynes at RSRE, I received an LCD panel. He also sent some elastomeric strips, which are pieces of rubber with densely-packed parallel, conductive needles. The panel was two sheets of thin glass that had been glued together with a small spacer between them. Close inspection revealed the nearly transparent conductive electrodes painted on the inner surfaces. Together with my assistant Keith Barraclough (we were both interns at Plessey), I designed the PCBs to mount the delicate glass panels and associated drive electronics. I wrote real-time software for a Z80 processor that generated the electrode waveforms. It was then relatively trival to get one chosen pixel in every column or every row activated. This is all that is needed for graph plotting of a single line. For more-advance plots, I generated ROM tables with various pre-computed pseudo-random sequences with known correlation patterns. Then, with appropriate selection of waveforms, it was possible to darken more than one pixel in a row or column at once without phantoms at the transposed cross points (based on the non-transitivity of correlation). My display had an area of about one inch by three. As everybody knows, LCD displays became a very important technology, especially for laptops and televisions. The LCD multiplexing problem was never really solved. Instead, modern display panels have transistors at every pixel and so the old scan multiplexing approach can be applied.     A mockup of the LCD display I used from an online image at RSRE. And also a schematic drawing of the panel structure.     A modern LCD oscilloscope.

As with quite a few technological developments conducted under the blanket of the Official Secrets Act, the UK technology was never properly exploited. Contrary to their contracts of employment, the good staff at RSRE did not get significant royalties from their inventions and I was told that they ultimately sued their employer (the UK government) for failing to maximise their benefit. I certainly did not get any money. Meanwhile, the Japanese companies Epson and Sharp took the lead.

Two or three years after this project, I saw the prototype LCD on display in the London Science Museum.

WHAT I DID MODERN IMPACT I constructed a CPU from a processor and DRAM chip and connected on various peripherals, including floppy and hard disks. I wrote a self-hosting C compiler and 68030 assembler and linker. I then implemented the unix kernel from scratch. At work I discovered source code for the Ultrix, the DEC version of unix, and so then could compile many of the standard shell utilities and ran them on my version of unix. Compared with Linus Torvalds, I did twice as much work since I created both the hardware and the software. PC hardware of the time was expensive and commonly lacked an MMU. But Linus' version, targeting PC hardware was ultimately far more successful since many people did have PC hardware and nobody else had my machine.     View of my home-made 68030 card with 16 MByte of DRAM     Linux developers did not create their own hardware: they waited until the PC specification evolved to included a sensible processor with an MMU.

When I had more-or-less finished, a student asked me about to explain some of the Minix code at the back of Tanenbaum's book. I had already met Tanenbaum and I had no problem understanding the code. But I wished I had seen the book earlier and simply copied Minix instead of starting from scratch. I used the resulting computer for about five years, before I switch to Linux. My first personal Linux computer had 4 MByte of RAM, which was less than the computer I had made, but it had richer software resources and I never looked back. But it was a while before the Linux sequencer implemented kernel timestamps on real-time MIDI traffic, just like I had implemented myself. (PROJECT : www.bigbrownbus.com/koo.corpus.cam.ac.old/projects/elencomputer/index.html)

WHAT I DID MODERN IMPACT I refactored all of the local EDA technology. I replaced the Cambridge HDL front end with a new Verilog parser (I learned about Verilog at Silicon Graphics where it was being used for TCP accelerator ASICs). The resulting tool was called CSYN. This told compiled Verilog RTL as input and rendering Xilinx Netlist Format (XNF) (and Cambridge HLD) as output code for input to the local simulators and Xilinx FPGA tools respectively. I also wrote a back end that output code for PALs such as the 16R8 and 22V10 that we widely used at that time, so these could also be programmed (by my widely used Unix-based PAL compiler (commercial tools were all hosted on MS DOS)) and simulated in a common Verilog environment. The benefits of the tool were rapidly and widely appreciated. The CSYN tool was used in a number of Cambridge companies (including Acorn) and also licensed to Motorola for use in their FPGA toolflow. I introduced Verilog to the Computer Science curriculum at Cambridge using my tool and along with a companion simulator. RTL is today, without question, the primary input mechanism for FPGAs from all vendors.     Schematic flow diagram of the inputs and outputs of the CSYN compiler.     Image of a modern RTL FPGA design flow environment

This was the first demonstration of such an RTL flow for FPGA. The work was published at the very first FPL conference the next year in Oxford. (PUBLICATION : www.cl.cam.ac.uk/~djg11/edadoc/cv2man/csyn-verilog-compiler.pdf)

WHAT I DID MODERN IMPACT With Brian Knight of Virata and Andrew Bird of Acorn, and at the prompting of Hermann Hauser, I had a meeting with Hugo Davenport of the local CATV company. He was managing director of Cambridge Cable (later NTL and then Virgin Media) and he gave us permission to install plant in their kerbside boxes throughout the town. We used dark fibres for head-end connection to the kerbside and diplexers to separate the 25.6 Mbps duplex final-drop data form the analogue CATV service, which could operate at the same time. I participated in standards developments for data over cable TV networks (DOCSIS) and later I worked on ADSL. In the UK today, these two techniques are the mainstay of residential broadband to the home. Broadband has become an important technology worldwide and is now considered a necessity. Video-on-demand has also recently taken off greatly: the last UK Blockbuster video rental shop closed in 2018. Today, young people often only watch television over the Internet, especially in the UK where the television license fee is imposed on broadcast services.     DJ Greaves standing next to a modern (2016) kerb side box while holding one of the prototype residential ADSL modems he designed at Virata.     Netflix is the predominant international Video-on-Demand service today, but we also have BBC iPlayer and the like from other broadcasters.

This project was way ahead of its time. About 20 years ahead, to be more precise. (PROJECT : www.cl.cam.ac.uk/~djg11/fromkoo/cambridge-itv-trial) (PUBLICATION : www.aes.org/e-lib/browse.cfm?elib=7091)

WHAT I DID MODERN IMPACT The Warren project at the Computer Laboratory designed and built a portfolio of some ten or so module designs. These included the LAN switches themselves and adaptors for Infra Red, Audio, Video and control. Even the doorbell was connected to demonstrate remote door unlocking. The Sonos corporation today makes a variety of audio LAN devices. Apple and others make them as well. There is a W3C standard protocol for streaming audio but different manufacturers' implementations are strangely incompatible. I wonder why!? Video doorbells and remote unlocking of the outer porch door are becoming everyday practice.     Schematic of the the Audio LAN installed at home of DJ Greaves in 1997.     A typical WiFi-connected audio component made by Sonos.

Although a large number of commercial approaches were made, in both directions, to license this technology, these ultimately failed since ATM LANs were seen as less attractive than Ethernet. Of course, if the ATM technology had been adopted, with its guaranteed quality-of-service, then all of today's terrible audio gaps and glitches would not be annoying everybody. (PROJECT : www.cl.cam.ac.uk/research/srg/han/Warren) (PUBLICATION : ieeexplore.ieee.org/document/660006)

WHAT I DID MODERN IMPACT I carefully measured the internal PCB dimensions and made my own drop-in replacement PCB. The new PCB had ADC and DAC components and packet framers to convey the audio over the LAN. To bring the system to life, my RA Daniel Gordon wrote a telephone exchange program that was hosted elsewhere on the network. The directors of Geemark flew to the UK to take a look and to discuss future prospects. But this project was ahead of its time. The Cisco Ethernet phone on your desk today is the direct modern equivalent.     Internal view of one of the phones with the new PCB installed.     An Ethernet-connected telephone set made by Cisco.

The phone was presented to the ATM Forum, Residential and Broadband working group, of which I was a founder. About 20 prototype instruments were made and some went to UCL and others to BT Martlesham. There's one in the central display cabinet on the top floor of the William Gates building. (PROJECT : www.bigbrownbus.com/koo.corpus.cam.ac.old/projects/warren)

WHAT I DID MODERN IMPACT I implemented CTOV, a design tool that took statically-allocated C code (no heap and bounded stack depth) and generated a circuit of equivalent functionality. Arrays were mapped to RAMs using automatic heuristics in the first instance, but the report file from one run could be manually edited and read in to a further run so that the engineer could trim this important aspect. The tool also supported various constructs from the SystemC library, such as thread starts and custom-precision integers. CTOV was licensed to industry and is currently fully owned by market leader Synopsis. Today there are many commercial and research compilers of this nature. These compilation flows are becoming widely used. A new execution platform has emerged with all the major cloud providers now adding FPGA chips to their server blades. Low energy execution has become the major driver for this technology. Performance increases are also commonly seen.     A fragment of C code that was very easy to compile to RTL.     Amazon promotional material for the FPGA-in-the-cloud elastic computing.

C-to-Gates is now called High-Level Synthesis (HLS). Contemporary, high-performance CPU cores use orders of magnitude more energy working out what to compute next than they use performing the computation. Because of this, the Von Neumann architecture is perhaps on its way out for big data. Analysis today, by Andre Dehon and others, predicts that hardware/FPGA execution will increasingly replace Von Neumann designs owing to reduced energy of execution. Certainly, the replacement of the fetch-execute cycle with circuit-switched wiring on FPGA has often been show to reduce computational energy use by two orders of magnitude (memory system energy use remains largely unchanged).

Scientific Acceleration on FPGA is the current major research direction for DJ Greaves, exemplified by the Kiwi project. (PROJECT : www.cl.cam.ac.uk/~djg11/cvtovpage-real) (PUBLICATION : ieeexplore.ieee.org/document/5970505)

WHAT I DID MODERN IMPACT The VTOC program compiled synthesiable RTL into C++ code. It had an advanced, incremental compilation approach, that carefully reflected the data dependencies between ports and hence could scale to model an entire chip as a single C++ module, albeit with millions of lines of code. A paper regarding VTOC was published at the Rapid Systems Prototyping conference in 2000. Subsequently a company was formed, Tenison EDA, that sold licenses to nearly all the major chip makers of the time. The VTOC approach is now commonly used throughout the IC industry where it is known as a 'virtual platform'. The use of FPGA hardware emulators has dropped off, these now being used only for hard-real-time applications like telecoms modems.     A single blade from a Zycad hardware emulation server.     A splash screen for a third-party toolset that integrated the VTOC compiler under the hood and attributes Tenison EDA.

Our startup received a large amount of coverage in Electronics Times, Electronics Weekly, Chip Design Magazine and other trade journals (that do not count towards academic citation indices). Articles were written both by technical journalists and staff at Tenison EDA. As is common for companies in the EDA space, Tenison was finally acquired by one of the large three EDA Vendors (Mentor, Synopsys and Cadence). (PUBLICATION : ieeexplore.ieee.org/abstract/document/855208)

WHAT I DID MODERN IMPACT This heating controller uses a novel model checking system called Pushlogic that still has no modern equivalent and is worthy of wider dissemination. Under Pushlogic, both the running applications and the interactions between sensors and actuators is modelled. When someone attempts to reconfigure the system, such as entering the home with a given app running on their phone, on-the-fly formal techniques prevent devices interfering with each other. Each time a new application was introduced into a 'domain-of-participation' automated model checking was activated to selectively bar parts of its behaviour and to ensure it can be controlled (e.g. speaker mute) under relevant conditions. This heating controller would now be called an 'Internet Of Things' device. A variety of companies now make such devices. These sometimes have advanced applications bundled with them. For instance, after I installed a Nest device in my daughter's house and her husband programmed it, she discovered the heating always automatically turned off when he left home! Accidental or deliberate? And for a door entry systems, a deployment embodying Pushlogic could ensure deadlock avoidance: it would ensure that you cannot lock all your entry keys inside the house when you are outside!     The heating controller and its block diagram.     Nest and Hive are two companies with IoT heating controllers. Note: they do not model check against adverse interactions with other home agents.

(PROJECT : www.cl.cam.ac.uk/research/srg/han/pebbles/datasheets/heatingcontroller)

WHAT I DID MODERN IMPACT Once the first version of the KiwiC compiler was working, we (S Singh and I) used it to generate a Smith Waterman accelerator on FPGA. A processing cell was defined that was easily paramaterisable in terms of how much of the search string it handled and an outer framework was defined that instantiated sufficient cells for the whole of the search string. The DNA to be searched was then streamed through these cells from the file server. Each component was a separate C# object. We presented a paper at the Many-Core and Reconfigurable Supercomputing Conference in Berlin. Our results for the HLS design were about one third the performance of a hand-crafted design on the same FPGA. This was because the Kiwi tool chain was immature. Papers are still being published accelerating Genome Sequencing on FPGA. Kiwi has also implemented Burrows-Wheeler searches. And a number of commercial FPGA-based accelerators are available for genomics processing have been sold. Today the hardware boxes are being replaced with AWS Elastic Computing: hiring FPGA can be cheaper than owning.     Basic structure of the Smith Waterman alignment algorithm.     Dragen workflow from a company that performs alignment and compression on FPGA

(PUBLICATION : www.semanticscholar.org/paper/Synthesis-of-a-Parallel-Smith-Waterman-Sequence-Greaves/9a9b4dc5d0921c4a4a6ffcaf40fb3e465c63e5d1)

WHAT I DID MODERN IMPACT The first CPU design was hand written in the RTL. The second design was again hand written, but in Bluespec RTL. I also wrote the Bluespec Compiler in FSharp. Both designs were loaded onto FPGA and demonstrated in my office to Mike Gordon and the rest of the Cake ML team. There is a massive demand for provably secure systems. A fresh start, like those of Kimmitt and Cake is a good approach, especially when performance penalties are tolerable. A recent example is home gateway firewalls. With broadband speeds in the tens of Mbps, the processing requirements for the firewall are modest and a relatively poor CPU implementation on an FPGA can well serve. But it must be completely secure. Engineers are turning to synthesised soft cores for this reason.     Cake ML CPU Initial Design     The Cake ML project is going from strength to strength.

I am currently working on techniques for advance processor synthesis from ISA specifications. I will return again to the current Cake ML specifications as a test case. (PROJECT : ieeexplore.ieee.org/abstract/document/7281847) (PUBLICATION : technotes-djg.blogspot.com/2013)